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* Edit or answer any Q&A by selecting Q&A number Hyper Link below + Write button (Save)
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ICACT20240441 Question.1
Questioner: 202212666@mail.sdu.edu.cn 2024-02-06 오전 12:09:38 |
ICACT20240441 Answer.1
Answer by Auhor jh.deng@saturn.yzu.edu.tw 2024-02-06 오전 12:09:38
Chrome  Click!! |
| What is the enhanced version of the REV method introduced for incrementally joint block tuning of subarrays, and how does it facilitate the calibration of large array antennas? |
First, sequentially execute the REV adjustments within each block, then perform the cumulative REV adjustments between blocks.
Example: Total 1x32 antenna elements with 4 blocks, each block contains 1x8 antenna elements. Thus, first, 1st block executes REV calibration. Next, the 2nd block and the calibrated 1st block execute the joint REV calibration. Then, using the cumulative REV calibration perform the 3rd block and 4th block antenna elements.
This adjustment utilizes the alignment strength energy provided by the preceding block to enhance the intensity value for REV within the next group block, thereby improving the tuning efficiency in the subsequent block.
Extending to large array antennas. Example: 4x32 antenna elements. It can be designed for 4 blocks. Each block contains 1x32 antenna elements.
Thus, using the previous example can adjust the first block 1x32 REV calibration. Next, 2nd block, 3rd block, and 4th block can be sequentially executed by REV adjustments.
Finally, Example: 32x32 antenna elements. It can be designed for 8 blocks. Each block contains 4x32 antenna elements. Similar to the previous procedures, the sequential REV adjustments can calibrate the 1st block, 2nd block, 3rd block, …, and 8th block antenna elements.
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ICACT20240441 Question.2
Questioner: madj0212@163.com 2024-02-07 오후 11:40:10 |
ICACT20240441 Answer.2
Answer by Auhor jh.deng@saturn.yzu.edu.tw 2024-02-07 오후 11:40:10
Chrome Click!! |
| What is the current cost of the technology? Can it continue to improve in the future? |
The current cost of the technology is the software computing time for the proposed enhanced REV algorithm. In the future, it can be improved by the hardware implementation. Moreover, we can use the DSP and logic circuit design, e.g., verilog code design, to realize REV algorithm and to accelerate the speed of the REV calibration. |
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